Design and optimization on reconfigurable butterfly core for a real-time FFT processor

• Published in: 2009 IEEE 8th International Conference on ASIC pp. 847 - 850
• Main Authors: Zhizhe Liu, Shunan Zhong, Yueyang Chen, Weinan Chu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2009
• Subjects: Atomic layer deposition; Atomic measurements; Bandwidth; Delay; Design optimization; Logic design; Microelectronics; Radix-2; Radix-4; Reconfigurable Butterfly Core; Reconfigurable logic; Runtime; Runtime Configurable FFT; Solids
• ISBN: 9781424438693; 1424438691; 1424438683; 9781424438686
• ISSN: 2162-7541; 2162-755X
• DOI: 10.1109/ASICON.2009.5351563

Runtime reconfigurable FFT processors on scale of data frame samples are being concerned and designed. A novel solution based on the reusable butterfly core is proposed for achievement of reconfigurable FFT processors. An alternative mixed fabric in radix-4 and radix-2 is applied to the proposed butterfly core. Parallel in-place memory access rule is proposed to fulfill the range of data frame sample scale, from 1024 to 16, with the recursive architecture of the single butterfly core. Implementation of the proposed FFT processor is under the technology of SMIC 0.18 ¿m CMOS, which gets to 3 ns on critical path and 2 mm 2 of a core area by reason of the optimization solution on data paths with 4-2 compressor clusters, instead of regular adders, and on data A, which is the data without rotation in the dragonfly core, with preprocessing.