A New Solution Based on Multi-rate LDPC for Flash Memory to Reduce ECC Redundancy

Low-density parity-check (LDPC) code can provide powerful error correcting performance for NAND flash memory. Different LDPC code rate has different error correcting performance. Moreover, the raw bit error rate of flash memory is very low in the early lifetime. This will generate ECC redundancy tha...

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Bibliographic Details
Published in2015 IEEE Trustcom/BigDataSE/ISPA Vol. 1; pp. 918 - 923
Main Authors Shigui Qi, Dan Feng, Nan Su, Wenguo Liu, Jingning Liu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.08.2015
Subjects
Ash
Decoding
ECC redundancy
Energy consumption
Error correction codes
flash memory
LDPC
Memory management
multi rate
Parity check codes
Redundancy
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DOI10.1109/Trustcom.2015.465

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Summary:Low-density parity-check (LDPC) code can provide powerful error correcting performance for NAND flash memory. Different LDPC code rate has different error correcting performance. Moreover, the raw bit error rate of flash memory is very low in the early lifetime. This will generate ECC redundancy that the error correcting performance of LDPC cannot be completely released. We propose a new Switch LDPC (S-LDPC) algorithm based on Multi-Rate LDPC code to reduce ECC redundancy and meet different error correcting requirement in the different periods of flash memory. S-LDPC algorithm can achieve optimal tradeoff among error correcting performance, decoding energy consumption and read performance. The extensive experiments show that S-LDPC algorithm can improve the average read response time of flash memory 25%-54% without reducing the reliability of flash memory. We further demonstrate that LDPC code with code rate 0.96 can save about 40% decoding energy consumption than LDPC code with code rate 0.7.
DOI:10.1109/Trustcom.2015.465