34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms

A 9,296µm 2 DEFLATE accelerator targeted for firmware decompression in battery-constrained IoT platforms is fabricated in 14nm tri-gate CMOS, and operates over a wide supply range of 210-900m V. Dual-ALU block-adaptive Huffman decoder enables simultaneous evaluation of a pair of code-lengths with op...

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Bibliographic Details
Published inESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) pp. 90 - 93
Main Authors Satpathy, Sudhir, Mathew, Sanu, Suresh, Vikram, Gopal, Vinodh, Guilford, James, Anders, Mark, Kaul, Himanshu, Agarwal, Amit, Hsu, Steven, Krisnnamurthy, Kam
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2018
Subjects
Decoding
decompression
DEFLATE
History
Huffman Decoder
Indexes
Microprogramming
Payloads
Throughput
Voltage measurement
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Summary:A 9,296µm 2 DEFLATE accelerator targeted for firmware decompression in battery-constrained IoT platforms is fabricated in 14nm tri-gate CMOS, and operates over a wide supply range of 210-900m V. Dual-ALU block-adaptive Huffman decoder enables simultaneous evaluation of a pair of code-lengths with opportunistic skipping of non-existent symbols improving throughput by 34% to 1.65Gb/s at 750mV, 25°C, while in-line literal packing and fenced-record generation achieves 63% memory bandwidth reduction for LZ77 reconstruction. Absence of register file and CAM circuits result in a fully-synthesizable implementation enabling ultra-low voltage operation with peak energy-efficiency of 1.56Tbps/W and 34.4Mbps throughput at 22µW total power consumption measured at 310mV.
DOI:10.1109/ESSCIRC.2018.8494238