A configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systems

• Published in: 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) pp. 1 - 4
• Main Authors: Laflamme-Mayer, N., Sawan, M., Blaquiere, Y.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2013
• Subjects: CMOS integrated circuits; Gain; Logic gates; MOS devices; Noise; Power supplies; Transistors
• ISBN: 146734897X; 9781467348973
• DOI: 10.1109/LASCAS.2013.6519083

A novel, configurable and compact CMOS analog buffer, dedicated to a wafer-scale prototyping platform for electronic systems is described in this paper. The proposed buffer architecture, made in a 0.18 μm CMOS technology, is based on complementary modified differential pairs combined with single current mirrors. This analog buffer can support a wide range of operating output voltages, from V DD - 150 mV down to V SS + 150 mV using a 3.3 V power supply. This design offers a configurable slew-rate, which range from 66 up to 450 V/μs and a quasi unity gain for all programmed slew-rates. This feature allows the user to adjust the proposed buffer to fit its needs while limiting noise injection in the power supply as well as quiescent current. Moreover, the proposed analog buffer supports a -3 dB bandwidth from 74 up to 194 MHz. The low count of transistors, 21, yields to a very compact structure that uses only 0.001824mm 2 of silicon area.