A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA

• Published in: 2013 23rd International Conference on Field programmable Logic and Applications pp. 1 - 4
• Main Authors: Tsusaka, Akihito, Izawa, Mai, Uno, Rie, Ozaki, Nobuyuki, Amano, Hideharu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2013
• Subjects: Arrays; Clocks; Delays; Hardware; Layout; Registers
• ISSN: 1946-147X; 1946-1488
• DOI: 10.1109/FPL.2013.6645594

Cool Mega Array (CMA) is an energy efficient Coarse Grained Reconfigurable processor Array (CGRA) consisting of a large PE (Processing Element) array. In order to reduce the power for storing intermediate results and clock tree, the PE array is consisting of combinatorial circuits. A hardware completion detection mechanism for CMA is proposed, implemented and evaluated. Each PE uses serially connected buffers with selectable taps, and the delay is decided according to the operation executed in the PE. Since the completion signal is transferred exactly on the same paths that for computation, the delay in the switch and wires are accounted. The post layout simulation revealed that the same performance without the mechanism can be obtained only with 5.1% area overhead and less than 6% extra power consumption. With the mechanism, a single micro-code can be used for various supply voltages to PE array.