On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture

• Published in: Eleventh IEEE European Test Symposium (ETS'06) pp. 239 - 246
• Main Authors: Poehl, F., Rzeha, J., Beck, M., Goessel, M., Arnold, R., Ossimitz, P.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2006
• Subjects: Circuit faults; Circuit testing; Compaction; Failure analysis; Integrated circuit testing; Logic devices; Logic testing; Performance evaluation; Production systems; System testing
• ISBN: 0769525660; 9780769525662
• ISSN: 1530-1877; 1558-1780
• DOI: 10.1109/ETS.2006.34

Technology and product ramp up suffers increasingly from systematic production defects. Diagnosis of scan test fail data plays an important role in yield enhancement as diagnosis of scan fail data helps to understand and overcome systematic production defects. Acquisition of scan fail data during high-volume production can lead to significant test time overhead. This paper presents a new on-chip architecture that evaluates scan test results and stores relevant scan diagnosis information on chip. Scan diagnosis data can be accessed after the scan test has finished with very little test time overhead. Moreover, the proposed technique is ATE independent. An implementation example, based on a state-of-the-art SoC device, is reported