3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics

Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low I OFF (< 2...

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Bibliographic Details
Published in2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial pp. 265 - 268
Main Authors Ernst, T., Bernard, E., Dupre, C., Hubert, A., Becu, S., Guillaumot, B., Rozeau, O., Thomas, O., Coronel, P., Hartmann, J.-M., Vizioz, C., Vulliet, N., Faynot, O., Skotnicki, T., Deleonibus, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2008
Subjects
CMOS
CMOS scaling
CMOS technology
Epitaxial growth
Etching
FinFET
FinFETs
Multichannel
Nanoelectronics
Nanowires
PhiFET
Robustness
Silicon
Tin
Transistors
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Summary:Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low I OFF (< 20 pA/mum) and high I ON (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer from discrete width layout constraints and can benefit from specific options like independent gate operation.
ISBN:9781424418107
1424418100
ISSN:2381-3555
2691-0462
DOI:10.1109/ICICDT.2008.4567292