Understanding barrier engineered charge-trapping NAND flash devices with and without high-K dielectric

Barrier engineered charge-trapping NAND flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multi-layer barrier is derived using WKB approximation. The rigorously derived analytical form is valid fo...

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Bibliographic Details
Published in2009 IEEE International Reliability Physics Symposium pp. 874 - 882
Main Authors Hang-Ting Lue, Sheng-Chih Lai, Tzu-Hsuan Hsu, Pei-Ying Du, Szu-Yu Wang, Kuang-Yeu Hsieh, Liu, R., Chih-Yuan Lu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2009
Subjects
Aluminum oxide
Barrier Engineering
BE-SONOS
Buffer layers
Charge carrier processes
Charge-trapping device
Electrons
Equations
High K dielectric materials
High-K gate dielectrics
modeling
NAND Flash
Nonvolatile memory
SONOS devices
Tunneling
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Summary:Barrier engineered charge-trapping NAND flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multi-layer barrier is derived using WKB approximation. The rigorously derived analytical form is valid for both electron and hole tunneling, as well as for any barrier composition. With this, the time evolution (Vt-time) of any BE-CTNF device during programming/erasing can be accurately simulated. The model is validated by experimental results from bandgap-engineered SONOS (BE-SONOS) and various structures using Al 2 O 3 top-capping layer. Using this model, various structures of BE-CTNF with high-K tunneling or blocking dielectric are investigated. Furthermore, the low-field tunneling current for various structures are simulated, providing theoretical foundations for retention and read disturb optimization.
ISBN:9781424428885
1424428882
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2009.5173370