Centralised Domain Based Faulty Node and Link Elimination in Hexagonal Node Based NoC

The NoC Architecture plays crucial role while designing communication systems for System on Chip (SoC). The NoC architecture is improved over conventional bus, shared bus design and cross bar interconnection architecture for on chip networks. In order to improve the Quality of Service, Congestion, T...

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Bibliographic Details
Published in2017 International Conference on Recent Advances in Electronics and Communication Technology (ICRAECT) pp. 100 - 104
Main Authors Gowda, Shilpa K., Rekha, K. R., Nataraj, K. R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2017
Subjects
arbiter
controller Domain
Dynamic reconfiguration
Field programmable gate arrays
FIFO
FPGA
Hexagonal pattern
Ipcore
Maintenance engineering
Monitoring
Network-on-chip
NoC
On chip Network
Router
Routing
SoC
Switch
Throughput
Topology
XY routing
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Summary:The NoC Architecture plays crucial role while designing communication systems for System on Chip (SoC). The NoC architecture is improved over conventional bus, shared bus design and cross bar interconnection architecture for on chip networks. In order to improve the Quality of Service, Congestion, Throughput and latency in NoC, Hexagonal node based architecture is proposed in our previous paper[14]. The challenge in the hexagonal node based NoC architecture is to eliminate the faulty link or node failure in the SoC without impacting the communication between node and maintain same throughput, latency and quality of service by converging the NoC. In this paper, we propose the effective approach to eliminate the faulty node or Links in NoC without impacting SoC functionality.
DOI:10.1109/ICRAECT.2017.53