Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation

This paper presents a hardware-oriented memory-limited online FastICA algorithm and its hardware architecture and implementation for eight-channel electroencephalogram (EEG) signal separation. The online algorithm integrates the data overlapping, garbage detection, channel permutation, and momentum-...

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Bibliographic Details
Published inICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) pp. 1438 - 1442
Main Authors Van, Lan-Da, Lu, Tsung-Che, Jung, Tzyy-Ping, Wang, Jo-Fu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2019
Subjects
and hardware implementation
Blind signal separation
component/channel switch
Computer architecture
Copper
EEG
Electroencephalography
fast independent component analysis (FastICA)
Hardware
Integrated circuits
Microsoft Windows
Signal processing algorithms
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Summary:This paper presents a hardware-oriented memory-limited online FastICA algorithm and its hardware architecture and implementation for eight-channel electroencephalogram (EEG) signal separation. The online algorithm integrates the data overlapping, garbage detection, channel permutation, and momentum-controlled weight update schemes to stabilize the order of the decomposed source signals across time. This study also realizes the algorithm into a hardware architecture and implementation with a core area of 1.469x1.469 mm 2 in a TSMC 90 nm process. The resulting power dissipation for eight-channel EEG signal separation is 65 mW@100 MHz at 1V.
ISSN:2379-190X
DOI:10.1109/ICASSP.2019.8682997