Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands

In order to provide high performance with low power consumption, modern multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage settings. Effective defect screening for the embedded cores in such multicore chips requires test application at th...

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Bibliographic Details
Published in2011 Asian Test Symposium pp. 33 - 39
Main Authors Kavousianos, X., Chakrabarty, K., Jain, A., Parekhji, R.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2011
Subjects
Dynamic voltage scaling
Job shop scheduling
Multicore processing
Schedules
SoC testing
Strontium
System-on-a-chip
test scheduling
Testing
voltage islands
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Summary:In order to provide high performance with low power consumption, modern multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage settings. Effective defect screening for the embedded cores in such multicore chips requires test application at their different operating voltages, which leads to higher test time and test cost. We propose a fast heuristic test scheduling technique for multicore chips that minimize the testing time when each core is tested at multiple voltage settings as well as if it is tested for state retention when the core switches between two voltage levels. Experimental results for two test-case SOCs from industry highlight the effectiveness of the proposed method.
ISBN:9781457719844
1457719843
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2011.53