Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs

State-of-the-art techniques for enhancing system-level reliability for SoCs include both design-time and run-time strategies, such as task mapping and reliable communication network design. In contrast to task mapping where the network topology is predefined, fault-tolerance in the communication net...

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Bibliographic Details
Published inProceedings / IEEE Computer Society Annual Symposium on VLSI pp. 619 - 624
Main Authors Zheng Wang, Littarru, Alessandro, Ugwu, Emmanuel Ikechukwu, Kanwal, Shazia, Chattopadhyay, Anupam
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2016
Subjects
Computer network reliability
Fault tolerance
Fault tolerant systems
Node Fault Tolerance
Reliability engineering
Reliability theory
System-level design
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Summary:State-of-the-art techniques for enhancing system-level reliability for SoCs include both design-time and run-time strategies, such as task mapping and reliable communication network design. In contrast to task mapping where the network topology is predefined, fault-tolerance in the communication network design involves the reliability evaluation of the network topology. In this paper, we apply the idea of k-node fault tolerant graph to address the challenge of reliable network design. To determine k-node fault tolerant graph for an arbitrary subject graph is non-trivial. We propose a heuristic based on divide-and-conquer approach and validate the quality of the results with an exhaustive search for small graphs. The effectiveness of proposed methodology is demonstrated with real multiprocessor computational task using a commercial system-level design environment.
ISSN:2159-3477
DOI:10.1109/ISVLSI.2016.40