Automatic generation of cycle-accurate Simulink blocks from hdl ips

• Published in: 2017 Forum on Specification and Design Languages (FDL) pp. 1 - 8
• Main Authors: Centomo, Stefano, Lora, Michele, Portaluri, Antonio, Stefanni, Francesco, Fummi, Franco
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2017
• Subjects: C++ languages; Co-simulation; Computational modeling; Functional Mock-up Interface; Hardware Description Languages; Hardware design languages; Indexes; Mathworks Simulink; Software packages
• DOI: 10.1109/FDL.2017.8303896

Simulation of accurate HW models is usually required to verify Embedded SW. However, heterogeneous system simulators do not easily allow it and designers must connect multiple simulators in complex co-simulation environments. This paper proposes the automatic generation of cycle-accurate Simulink blocks from the two most popular HW description languages: VHDL and Verilog. The methodology starts from an IP modeled in one of the two supported HW description languages. Then, it relies on state-of-the-art RTL models abstraction procedure to produce a functionally equivalent cycle-accurate model of the IP. Then, it proposes two alternative mapping and code-generation techniques. The first one relies on the portable FMI standard, while the other one exploits Mathworks' proprietary C MEX S-Functions. These blocks can be easily integrated within Simulink to simulate digital HW components while avoiding to build complex and computationally demanding co-simulation frameworks: a valuable feature when developing complex heterogeneous systems. A set of RTL IPs are used to compare the proposed approach to state-of-the-art co-simulation techniques. Furthermore, the experiments presented in this paper compares the two proposed alternatives to highlight their advantages and drawbacks.