All-digital hybrid temperature sensor network for dense thermal monitoring

• Published in: 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers pp. 260 - 261
• Main Authors: Seungwook Paek, Wongyu Shin, Jaeyoung Lee, Hyo-Eun Kim, Jun-Seok Park, Lee-Sup Kim
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2013
• Subjects: Clocks; Program processors; Temperature distribution; Temperature measurement; Temperature sensors
• ISBN: 9781467345156; 1467345156
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2013.6487726

Technology scaling and many-core design trends demand detailed information regarding the spatial temperature distribution, which is essential for dynamic thermal management [1,2]. The number of on-chip temperature sensors in high-performance processors is increasing, with state-of-the-art commercial processors embedding up to 44 on-chip sensors [3] and the number is likely to increase in the future (Fig. 14.7.1(a)). We observe two significant challenges in on-chip temperature sensing: 1) the increasing number of sensors, and 2) placing them in a regular manner (not solely on the potential hotspots). The number of sensors is mostly constrained by their area. Indeed, the sensor area is difficult to shrink since large delay lines or a BJT with a large ADC, and digital circuits are required to generate a proportional-to-absolute-temperature (PTAT) signal [2,5,6]. Many-core processor architectures give rise to the second challenge, namely, the hotspot locations within many-core processors are difficult to predict since we cannot determine the task allocation (and heat) profile at design time [2]. Consequently, an area-efficient dense thermal monitoring technique is desirable for next-generation processors.