Energy-efficient high-speed links using BER-optimal ADCs

We recently explored the concept of using BER-optimal ADCs for high-speed links. In this paper, we study the benefits of BER-optimal ADCs in terms of power savings and relaxation of component specifications in a 90 nm 1.2V CMOS process. These analyses are based on component models for a flash ADC th...

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Bibliographic Details
Published in2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) pp. 1 - 4
Main Authors Yingyan Lin, Aolin Xu, Shanbhag, N., Singer, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2011
Subjects
Ash
Bandwidth
Bit error rate
Clocks
Gain
Latches
Power demand
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Summary:We recently explored the concept of using BER-optimal ADCs for high-speed links. In this paper, we study the benefits of BER-optimal ADCs in terms of power savings and relaxation of component specifications in a 90 nm 1.2V CMOS process. These analyses are based on component models for a flash ADC that capture bandwidth limitation of pre-amplifiers and metastability of latches. We show that in the presence of these ADC non-idealities, a 3-bit BER-optimal ADC can provide a 3 dB ADC shaping gain over a 4-bit conventional ADC. The one bit reduction offers power savings of 75% in the VGA and 50% in the ADC. Further, the 3dB ADC shaping gain can be traded-off for a 50% reduction of transmit driver power, a 75% reduction of the pre-amplifier bandwidth, or a saving of one latch stage that leads to a 20% additional power reduction in the ADC.
ISBN:9781467322881
1467322881
ISSN:2151-1225
2151-1233
DOI:10.1109/EDAPS.2011.6213750