A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array

• Published in: 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers pp. 56 - 57
• Main Authors: Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming'e Jing, Xiaoyang Zeng, Zhiyi Yu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2013
• Subjects: Arrays; Clocks; Energy efficiency; Multimedia communication; Program processors; Registers; Synchronization
• ISBN: 9781467345156; 1467345156
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2013.6487635

With the increasing complexity and variety of applications, programmable multi-core processors are drawing attention due to their high flexibility and low implementation cost, yet their performance and energy efficiency still cannot fulfill the demands of many compute-intensive applications. This paper describes a high-performance energy-efficient 24-core processor for multi-media and communication applications, with the following key features: (1) a packet-controlled circuit-switched double-layer network-on-chip (NoC) which provides 11Tb/s/W energy efficiency with 435Gb/s bisection-bandwidth; (2) a cluster-shared NoC-connected heterogeneous reconfigurable execution array, which can improve the performance of frequently used computations in multimedia and communication applications by over 6×; (3) memory hierarchy improvements, including a multi-page foreground and background register file, and memory splitting and sharing. The processor, implemented in TSMC 65nm CMOS LP and occupying 18.8mm 2 (Fig. 3.6.7) operates at 850MHz at 1.2V, with 523mW power dissipation and 39GOPS/W (26pJ/operation) energy efficiency, which is 1.75× better than our former 16-core processor [3].