Highly Reliable Flash Memory with Self-Aligned Split-Gate Cell Embedded into High Performance 65nm CMOS for Automotive & Smartcard Applications

• Published in: 2012 4th IEEE International Memory Workshop pp. 1 - 4
• Main Authors: Shum, D., Power, J. R., Ullmann, R., Suryaputra, E., Ho, K., Hsiao, J., Tan, C. H., Langheinrich, W., Bukethal, C., Pissors, V., Tempel, G., Rohrich, M., Gratz, A., Iserhagen, A., Andersen, E. O., Paprotta, S., Dickenscheid, W., Strenz, R., Duschl, R., Kern, T., Hsieh, C. T., Huang, C. M., Ho, C. W., Kuo, H. H., Hung, C. W., Lin, Y. T., Tran, L. C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2012
• Subjects: CMOS integrated circuits; Computer architecture; Logic gates; Microprocessors; Reliability; Split gate flash memory cells
• ISBN: 9781467310796; 1467310794
• ISSN: 2159-483X
• DOI: 10.1109/IMW.2012.6213670

A split-gate (SG) flash memory cell has been embedded in a 65nm ground-rule high performance (HP) CMOS logic process with copper low K interconnects. A gate spacer processing sequence self-aligned (SA) process provides a reliability-robust cell and high degree of modularity with one extra mask to form the SG structure. The proposed cell is optimized for minimum module area overhead, high endurance and can be integrated in a standard stacked gate Technology in a modular way.