Design and Analysis of a New 31-Level Asymmetrical Multilevel Inverter Topology with Different PWM Techniques

• Published in: 2018 3rd International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity (CIPECH) pp. 1 - 7
• Main Authors: Gupta, Shubham Kumar, Rathore, Kuldeep, Bansal, Praveen
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2018
• Subjects: Asymmetric Multilevel Inverter (ASMLI); Frequency modulation; Inverters; Pulse width modulation; Pulse Width Modulation (PWM); Switches; Topology; Total harmonic distortion; Total Harmonic Distortion (THD)
• DOI: 10.1109/CIPECH.2018.8724251

This paper presents an asymmetrical multilevel inverter topology with different pulse width modulation technique. The main objective of this paper is to increase the number of levels at the output voltage with less switches used. This proposed topology offers high power capability associated with less commutation losses, less total harmonic distortion (THD), and involves less number of switching devices and less number of voltage source in comparison of conventional topologies for 31-Level asymmetric multilevel inverter. This topology used asymmetric voltage sources is in nature, that required four asymmetric voltage sources and ten switching devices for producing 31-Level single phase output voltage. This paper presents the comparison of total harmonic distortion for different pulse width modulation technique, with different modulation index, and the simulation result of proposed topology for single phase 31-level multilevel inverter, which are carried out by using MATLAB/Simulink R2013a software version.