Reliability investigation of T-RAM cells for DRAM applications

In this work, we present a reliability investigation of T-RAM cells, considering their read failure, data retention and endurance. Experimental results on decananometer devices reveal a successful cell operation solving the voltage trade-off for optimal performance on state-0 and state-1, whose orig...

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Published in2014 IEEE International Reliability Physics Symposium pp. MY.8.1 - MY.8.4
Main Authors Mulaosmanovic, Halid, Paolucci, Giovanni M., Compagnoni, Christian Monzio, Castellani, Niccoló, Carnevale, Gianpietro, Fantini, Paolo, Ventrice, Domenico, Viganó, Sara, Conti, Anna M., Righetti, Niccolo, Spinelli, Alessandro S., Lacaita, Andrea L., Benvenuti, Augusto, Grossi, Alessandro
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2014
Subjects
Anodes
forward-breakover
gated-thyristors
Logic gates
nanoscale semiconductor devices
Performance evaluation
Random access memory
Reliability
Resistance
semiconductor-device modeling
T-RAM
Temperature measurement
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Summary:In this work, we present a reliability investigation of T-RAM cells, considering their read failure, data retention and endurance. Experimental results on decananometer devices reveal a successful cell operation solving the voltage trade-off for optimal performance on state-0 and state-1, whose origin is explained by clear pictures of the physical processes giving rise to read failure and limiting data retention. Moreover, endurance results appear very promising, with cell functionality preserved up to very high cycling doses.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2014.6861162