Parallel nonvolatile programming of power-up states of SRAM cells

In this paper, we propose a parallel programmable non-volatile memory using an ordinary static random access memory (SRAM). Parallel non-volatile programming of the power-up states of the entire SRAM array is achieved by simply applying high-voltage stress to the power supply terminal after storing...

Full description

Saved in:
Bibliographic Details
Published in2017 IEEE 12th International Conference on ASIC (ASICON) pp. 418 - 421
Main Authors Hiramoto, Toshiro, Mizutani, Tomoko, Takeuchi, Kiyoshi, Kobayashi, Masaharu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2017
Subjects
Programming
SRAM cells
Stress
Two dimensional displays
Online AccessGet full text

Cover

More Information
Summary:In this paper, we propose a parallel programmable non-volatile memory using an ordinary static random access memory (SRAM). Parallel non-volatile programming of the power-up states of the entire SRAM array is achieved by simply applying high-voltage stress to the power supply terminal after storing inverted desired data in the SRAM array. Successful 2kbit non-volatile programming and recalling of the power-up states are demonstrated using a device-matrix-array (DMA) test element group (TEG) fabricated by 0.18 μm technology.
DOI:10.1109/ASICON.2017.8252502