Non-binary SAR ADC with digital error correction for low power applications

This paper describes techniques for creating a low-power SAR ADC with an error-correcting non-binary successive approximation algorithm; it is suitable for low power applications, performs digital error correction, and does not require analog calibration. Two techniques have been proposed for implem...

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Bibliographic Details
Published inAPCCAS 2010-2010 IEEE Asia Pacific Conference on Circuits and Systems pp. 196 - 199
Main Authors Ogawa, T, Matsuura, T, Kobayashi, H, Takai, N, Hotta, M, San, H, Abe, A, Yagi, K, Mori, T
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2010
Subjects
Algorithm design and analysis
Approximation algorithms
Calibration
Comparator
Digitally-assisted analog technology
Error correction
Low power
Noise
Non-binary
Power demand
Redundancy
SAR ADC
Simulation
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Summary:This paper describes techniques for creating a low-power SAR ADC with an error-correcting non-binary successive approximation algorithm; it is suitable for low power applications, performs digital error correction, and does not require analog calibration. Two techniques have been proposed for implementing low-power SAR ADCs: use of two comparators, and a charge-sharing architecture. However these techniques would normally require analog calibration of comparator offsets. Here we propose a non-binary SA algorithm that compensates for comparator offset effects in the digital domain, and so eliminates the need for analog calibration. Results of our Matlab simulation validate the effectiveness of this approach.
ISBN:142447454X
9781424474547
DOI:10.1109/APCCAS.2010.5774747