A Data erasing Writing technique based 1T1M Quaternary Memory Circuit Design

Memristor is a newly fabricated device which is becoming very popular among the researchers for its nonvolatility, nanometer size and good switching behavior. In this work- Memristor-MOS hybrid architecture based Quaternary memory array design with complete read write technique has been developed. E...

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Bibliographic Details
Published in2018 10th International Conference on Electrical and Computer Engineering (ICECE) pp. 317 - 320
Main Authors Biswas, Baishakhi Rani, Harun-Ur-Rashid, A.B.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2018
Subjects
Cell size
Computer architecture
Integrated circuit modeling
Memristor
Memristors
Microprocessors
MOSFET
Non-volatility
Switching Speed
Threshold voltage
Transistors
Writing
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Summary:Memristor is a newly fabricated device which is becoming very popular among the researchers for its nonvolatility, nanometer size and good switching behavior. In this work- Memristor-MOS hybrid architecture based Quaternary memory array design with complete read write technique has been developed. Each cell contains only one Memristor and a Transistor and is able to store two bits of memory in the single cell. The proposed writing technique for this design is data erasing based which reduces circuit complexity by avoiding feedback read-based writing technique. The verification of the proposed design has been achieved through LTSPICE simulation and the design shows superiority in terms of compactness, acceptable noise margin and simplicity in operation.
DOI:10.1109/ICECE.2018.8636774