A novel SAT-based ATPG approach for transition delay faults

Along with advances in modern VLSI technology, delay faults are becoming ever more important. On the other hand, the strength of SAT-solver engines has made them an attractive means for solving many Computer Aided Design (CAD) problems. This paper presents a new SAT-based Automatic Test Pattern Gene...

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Bibliographic Details
Published in2017 IEEE International High Level Design Validation and Test Workshop (HLDVT) pp. 17 - 22
Main Authors Zokaee, Farzaneh, Sabaghian-Bidgoli, Hossein, Janfaza, Vahid, Behnam, Payman, Navabi, Zainalabedin
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2017
Subjects
ATPG
Automatic test pattern generation
Circuit faults
Delays
Encoding
Fault coverage
Integrated circuit modeling
Logic gates
SAT
Transition delay fault
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Summary:Along with advances in modern VLSI technology, delay faults are becoming ever more important. On the other hand, the strength of SAT-solver engines has made them an attractive means for solving many Computer Aided Design (CAD) problems. This paper presents a new SAT-based Automatic Test Pattern Generation (ATPG) approach targeting transition delay faults using a novel 8-value encoding system. Experimental results demonstrate that our novel SAT-based approach requires the generation of fewer number of test vectors in comparison with the state of the art works with the same fault coverage. In addition, by increasing the number of test patterns, the proposed method can achieve better fault coverage compared to the existing works. The whole process of test generation has been performed in a reasonable time.
ISSN:2471-7827
DOI:10.1109/HLDVT.2017.8167458