Design of multi-threaded processor's pause mechanism

This paper presents three pause mechanisms of multi-threaded processors (micro-engine) of network processor, which is mainly used for dealing with reference instruction. We implement design of RTL-level code, functional simulation and logic synthesis on these three mechanisms. At last according to f...

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Bibliographic Details
Published in2011 International Conference on Electronics, Communications and Control (ICECC) pp. 1416 - 1419
Main Authors Pei-Jun Ma, Meng Liu, Yu-Jia Peng, Kang Li, Jiang-Yi Shi
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2011
Subjects
Analytical models
Clocks
Engines
Hardware
Instruction sets
multi-threaded processor
pause
Pipelines
reference instruction
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Summary:This paper presents three pause mechanisms of multi-threaded processors (micro-engine) of network processor, which is mainly used for dealing with reference instruction. We implement design of RTL-level code, functional simulation and logic synthesis on these three mechanisms. At last according to frequency and hardware resources and the expected performance requirements we select pause method based on state machine as the pause mechanism of micro-engine. This method ensures effective functional integrity of the micro-engine and meets prospective requirements of design.
ISBN:1457703203
9781457703201
DOI:10.1109/ICECC.2011.6066711