Low Power Probabilistic Floating Point Multiplier Design

We present a low power probabilistic floating point multiplier. Probabilistic computation has been shown to be a technique for achieving energy efficient designs. As best known to the authors, this is the first attempt to use probabilistic digital logic to attain low power in a floating point multip...

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Bibliographic Details
Published in2011 IEEE Computer Society Annual Symposium on VLSI pp. 182 - 187
Main Authors Gupta, A., Mandavalli, S., Mooney, V. J., Keck-Voon Ling, Basu, A., Johan, H., Tandianus, B.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2011
Subjects
Adders
Arrays
Error analysis
floating point multiplication
Hardware design languages
Logic gates
probabilistic computation
Probabilistic logic
Ray tracing
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Summary:We present a low power probabilistic floating point multiplier. Probabilistic computation has been shown to be a technique for achieving energy efficient designs. As best known to the authors, this is the first attempt to use probabilistic digital logic to attain low power in a floating point multiplier. To validate the approach, probabilistic multiplications are introduced in a ray tracing algorithm used in computer graphics applications. It is then shown that energy savings of around 31% can be achieved in a ray tracing algorithm's floating point multipliers with negligible degradation in the perceptual quality of the generated image.
ISBN:9781457708039
1457708035
ISSN:2159-3469
2159-3477
DOI:10.1109/ISVLSI.2011.54