Power Analysis and Reduction Techniques for Transition Fault Testing

• Published in: 2008 17th Asian Test Symposium pp. 403 - 408
• Main Authors: Agarwal, K., Vooka, S., Ravi, S., Parekhji, R., Gill, A.S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2008
• Subjects: Automatic control; Automatic test pattern generation; Circuit faults; Circuit testing; Clock Gates; Design for testability; Energy consumption; Lab-on-a-chip; Launch off Capture; Launch off Shift; Silicon; Switching circuits; Test Power; Thin film transistors; Transition Fault Test
• ISBN: 0769533965; 9780769533964
• ISSN: 1081-7735; 2377-5386
• DOI: 10.1109/ATS.2008.86

This paper examines the differences in power consumption characteristics of two popular ATPG techniques for transition fault testing (TFT) -- launch off shift (LOS) and launch off capture (LOC). These differences have critical implications on the circuit switching during the launch and capture cycles, and if unaddressed, can lead to IR drop issues and unwarranted silicon failures. Our investigations show that power consumption in the launch cycle for LOS patterns can be as high as 1.96 times the corresponding number for LOC patterns. We systematically understand the reasons for this difference and propose a variety of power-aware design-for-test (DFT) and automatic test pattern generation (ATPG) techniques to limit this power differential as well as general TFT power consumption. The proposed techniques include use of (a) fill techniques, (b) intelligent test and functional enable control of clock gates, and (c) pattern re-generation using low compression and low effort ATPG. Our experiments demonstrate the efficacy of the proposed techniques in reducing power consumption, and the associated trade-offs in pattern volume.