Analog transaction level modeling

In this paper, we present a new abstraction technique that extends the existing verification methodologies OVM [2] and UVM to the analog domain. This abstraction technique is referred to as Analog Transaction Level Modeling.

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Bibliographic Details
Published in2011 IEEE International High Level Design Validation and Test Workshop p. 82
Main Authors Rath, A. W., Esen, V., Ecker, W.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2011
Subjects
Buildings
Data models
Design methodology
Electronic mail
Integrated circuit modeling
Time frequency analysis
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Summary:In this paper, we present a new abstraction technique that extends the existing verification methodologies OVM [2] and UVM to the analog domain. This abstraction technique is referred to as Analog Transaction Level Modeling.
ISBN:1457717441
9781457717444
ISSN:1552-6674
2471-7827
DOI:10.1109/HLDVT.2011.6114171