A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture

To reduce the test application time and the test data volume in full-scan testing, various methods are proposed which utilize some additional built-in circuits dedicated for testing. In contrast, a previous method, called Reduced Scan Shift, does not utilize any additional built-in hardware. However...

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Bibliographic Details
Published in14th Asian Test Symposium (ATS'05) pp. 366 - 371
Main Authors Shinogi, T., Yamada, H., Hayashi, T., Tsuruoka, S., Yoshikawa, T.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2005
Subjects
Circuit faults
Circuit testing
Computer architecture
Costs
Data engineering
Electronic equipment testing
Electronic mail
Flip-flops
Hardware
Large scale integration
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Summary:To reduce the test application time and the test data volume in full-scan testing, various methods are proposed which utilize some additional built-in circuits dedicated for testing. In contrast, a previous method, called Reduced Scan Shift, does not utilize any additional built-in hardware. However, the method relies on scan chain flip-flop reordering, which is not always applicable. In this paper, we propose a test data sequence generation method for Reduced Scan Shift without scan chain flip-flop reordering. Our method fully utilizes justification technique and don't-care bits in test vectors.
ISBN:0769524818
9780769524818
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2005.17