Very Low Voltage (VLV) Design

This paper is a tutorial-style introduction to a special session on: Effective Voltage Scaling in the Late CMOS Era. It covers the fundamental challenges and associated solution strategies in pursuing very low voltage (VLV) designs. We discuss the performance and system reliability constraints that...

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Published in2017 IEEE International Conference on Computer Design (ICCD) pp. 601 - 604
Main Authors Bertran, Ramon, Bose, Pradip, Brooks, David, Burns, Jeff, Buyuktosunoglu, Alper, Chandramoorthy, Nandhini, Cheng, Eric, Cochet, Martin, Eldridge, Schuyler, Friedman, Daniel, Jacobson, Hans, Joshi, Rajiv, Mitra, Subhasish, Montoye, Robert, Paidimarri, Arun, Parida, Pritish, Skadron, Kevin, Stan, Mircea, Swaminathan, Karthik, Vega, Augusto, Venkataramani, Swagath, Vezyrtzis, Christos, Gu-Yeon Wei, Wellman, John-David, Ziegler, Matthew
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2017
Subjects
Energy efficiency
frequency scaling
low power design
Low voltage
Optimization
Program processors
Random access memory
real-time performance
Reliability
Resilience
system reliability
voltage scaling
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Summary:This paper is a tutorial-style introduction to a special session on: Effective Voltage Scaling in the Late CMOS Era. It covers the fundamental challenges and associated solution strategies in pursuing very low voltage (VLV) designs. We discuss the performance and system reliability constraints that are key impediments to VLV. The associated trade-offs across power, performance and reliability are helpful in inferring the optimal operational voltage-frequency point. This work was performed under the auspices of an ongoing DARPA program (named PERFECT) that is focused on maximizing system-level energy efficiency.
ISSN:1063-6404
2576-6996
DOI:10.1109/ICCD.2017.105