An Effective Design for Hierarchical Test Generation Based on Strong Testability

Hierarchical test generation is an efficient method of test generation for VLSI circuits. In this paper, we study a test plan generation algorithm for hierarchical test based on strong testability. We propose a heuristic algorithm for finding a control forest requiring a small number of hold functio...

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Bibliographic Details
Published in14th Asian Test Symposium (ATS'05) pp. 288 - 293
Main Authors Ichihara, H., Okamoto, N., Inoue, T., Hosokawa, T., Fujiwara, H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2005
Subjects
Circuit testing
datapath
Design for testability
Educational institutions
Hardware
Heuristic algorithms
Hierarchical test generation
Logic circuits
Logic design
Logic testing
strong testability
test plan
Time sharing computer systems
Very large scale integration
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Summary:Hierarchical test generation is an efficient method of test generation for VLSI circuits. In this paper, we study a test plan generation algorithm for hierarchical test based on strong testability. We propose a heuristic algorithm for finding a control forest requiring a small number of hold functions by improving an existing test plan generation algorithm based on strong testability. Experimental results show that the proposed algorithm is effective in reducing additional hold functions, i.e., reducing hardware overhead and delay penalty of datapaths
ISBN:0769524818
9780769524818
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2005.23