Design of a current steering CMOS D/A converter with an adaptive control switch and a novel layout technique

• Published in: 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial pp. 29 - 32
• Main Authors: Junho Moon, Sanghoon Hwang, Daeyoon Kim, Heewon Kang, Seungjin Yeo, Doobock Lee, Minkyu Song
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2008
• Subjects: Adaptive control; Alpha-Power Law; Analog circuits; CMOS analog integrated circuits; CMOS process; CMOS technology; Current Steering; DAC; Fabrication; MOSFET circuits; Semiconductor device modeling; Small Area; Switches; Switching converters
• ISBN: 9781424418107; 1424418100
• ISSN: 2381-3555; 2691-0462
• DOI: 10.1109/ICICDT.2008.4567239

While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power law model. In order to improve the matching characteristics of the DAC current cell, moreover, we introduce a new and unique adaptive-control-switch (ACS) and a common current cell layout technique using a tournament algorithm. The prototype circuit has been fabricated with a Samsung 1.8 V, 0.18 mum, 1-poly, 5-metal CMOS technology. It occupies 0.52 mm 2 of silicon area with 15.8 mW power consumption. The fabricated chip area and the measured power dissipation are reduced by 30% and 25% over conventional ones, respectively.