Accelerator-rich CMPs: From concept to real hardware

• Published in: 2013 IEEE 31st International Conference on Computer Design (ICCD) pp. 169 - 176
• Main Authors: Yu-Ting Chen, Cong, Jason, Ghodrat, Mohammad Ali, Huang, Muhuan, Chunyue Liu, Bingjun Xiao, Yi Zou
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2013
• Subjects: Acceleration; computer architecture; customizable computing; Data transfer; design automation; Field programmable gate arrays; FPGA; Hardware; Program processors; prototyping; Resource management; System-on-chip
• ISSN: 1063-6404; 2576-6996
• DOI: 10.1109/ICCD.2013.6657039

Application-specific accelerators provide 10-100× improvement in power efficiency over general-purpose processors. The accelerator-rich architectures are especially promising. This work discusses a prototype of accelerator-rich CMPs (PARC). During our development of PARC in real hardware, we encountered a set of technical challenges and proposed corresponding solutions. First, we provided system IPs that serve a sea of accelerators to transfer data between userspace and accelerator memories without cache overhead. Second, we designed a dedicated interconnect between accelerators and memories to enable memory sharing. Third, we implemented an accelerator manager to virtualize accelerator resources for users. Finally, we developed an automated flow with a number of IP templates and customizable interfaces to a C-based synthesis flow to enable rapid design and update of PARC. We implemented PARC in a Virtex-6 FPGA chip with integration of platform-specific peripherals and booting of unmodified Linux. Experimental results show that PARC can fully exploit the energy benefits of accelerators at little system overhead.