Improving Network Processing Dependability with Heterogeneous Reliability Cores

• Published in: 2009 International Conference on Communication Software and Networks pp. 479 - 483
• Main Authors: Ungsunan, P.D., Chuang Lin, Xiangzhen Kong, Yi Gai
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2009
• Subjects: Computer architecture; Computer network reliability; dependability; Embedded software; Hardware; heterogeneous multi-core; Multicore processing; Power system reliability; reliability; Risk management; Software performance; Telecommunication network reliability; Voltage
• ISBN: 9780769535227; 0769535224
• DOI: 10.1109/ICCSN.2009.147

An emerging problem facing future high-performance embedded multi-core and network processors are transient faults caused by radiation, noise and other factors.These faults will likely make future multi-core processors less reliable as chip features shrink, voltages decrease, and the number of cores increase. To address this problem, we propose a systems approach of managing and allocating reliability according to software process requirements. The heterogeneous multi-core architecture proposed is based on cores with differing reliabilities. Critical and non-critical software components are segregated and matched with the higher and lower reliability cores, respectively. This method is applied to a network processing example and we show that by using heterogeneous reliability cores the overall system failure rate can be reduced significantly, while offering the same or better overall performance, power utilization and chip area as symmetric cores.