A VLSI architecture for the K-best Sphere-Decoder in MIMO systems

This article presents a VLSI architecture for the K-best Sphere-Decoder (K-best SD) algorithm as a hard-output detector in the context of SM-MIMO (Spatial Multiplexing Multiple-Input Multiple-Output) systems immersed in Rayleigh fading channels. The design and implementation of its corresponding dat...

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Bibliographic Details
Published in2012 International Conference on Reconfigurable Computing and FPGAs pp. 1 - 6
Main Authors Cervantes-Lozano, P., Gonzalez-Perez, L. F., Garcia-Garcia, A. D.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2012
Subjects
Bit error rate
Complexity theory
Computer architecture
Fading
hard-output detection
K-best Sphere-Decoder
MIMO
MIMO systems
Rayleigh fading channels
Signal processing algorithms
Vectors
VLSI architectures
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Summary:This article presents a VLSI architecture for the K-best Sphere-Decoder (K-best SD) algorithm as a hard-output detector in the context of SM-MIMO (Spatial Multiplexing Multiple-Input Multiple-Output) systems immersed in Rayleigh fading channels. The design and implementation of its corresponding data-path and control-path components over FPGA devices are considered. Results on synthesis, bit error rate performance, and data throughput are reported.
ISBN:1467329193
9781467329194
ISSN:2325-6532
2640-0472
DOI:10.1109/ReConFig.2012.6416791