Double-gate SOI devices for low-power and high-performance applications

• Published in: ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 pp. 217 - 224
• Main Authors: Roy, K., Mahmoodi, H., Mukhopadhyay, S., Ananthan, H., Bansal, A., Cakici, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Capacitance; FinFETs; Logic circuits; Logic devices; Manufacturing; Nanoscale devices; Operational amplifiers; Power dissipation; Scalability; Trigger circuits
• ISBN: 078039254X; 9780780392540
• ISSN: 1092-3152; 1558-2434
• DOI: 10.1109/ICCAD.2005.1560067

Double-gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG devices, quasi-planar SOI FinFETs are easier to manufacture compared to planar double-gate devices. DG devices with independent gates (separate contacts to back and front gates) have recently been developed. DG devices with symmetric and asymmetric gates have also been demonstrated. Such device options have direct implications at the circuit level. Independent control of front and back gate in DG devices can be effectively used to improve performance and reduce power in sub-50nm circuits. Independent gate control can be used to merge parallel transistors in noncritical paths. This results in reduction in the effective switching capacitance and hence power dissipation. We show a variety of circuits in logic and memory that can benefit from independent gate operation of DG devices. As examples, we show the benefit of independent gate operation in circuits such as dynamic logic circuits, Schmitt triggers, sense amplifiers, and SRAM cells. In addition to independent gate option, we also investigate the usefulness of asymmetric devices and the impact of width quantization and process variations on circuit design.