An Analysis of Parallel Prefix Adders Regarding the Design of Low-Power Data Oriented Adders

The paper presents results of detailed analysis of power dissipated by parallel prefix adders when operating on specific data. Using extended model of CMOS gate power consumption deepened analysis can be done. The model take into consideration changes of input vectors, not only switching activity of...

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Bibliographic Details
Published in2018 International Conference on Signals and Electronic Systems (ICSES) pp. 7 - 12
Main Author Brzozowski, Ireneusz
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2018
Subjects
Adders
Capacitance
circuit activity
CMOS technology
Integrated circuit modeling
Layout
layout design
Logic gates
low-power adder
parallel prefix adder
Power dissipation
power dissipation assessment
Semiconductor device modeling
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Summary:The paper presents results of detailed analysis of power dissipated by parallel prefix adders when operating on specific data. Using extended model of CMOS gate power consumption deepened analysis can be done. The model take into consideration changes of input vectors, not only switching activity of signals. In the research several structures of adders have been analyzed with various scenarios of input data. Results show that for different kind of summed data different structures of adders are better considering reduction of power consumption.
ISSN:2474-2465
DOI:10.1109/ICSES.2018.8507292