Embedded flash testing: overview and perspectives

The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like flash. Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. In this paper, we present a...

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Bibliographic Details
Published in2006 International Conference on Design & Test of Integrated Systems in Nanoscale Technology : IEEE DTIS 2006 : September 05-07, 2006, Tunis, Tunisia : proceedings pp. 210 - 215
Main Authors Ginez, O., Daga, J.-M., Girard, P., Landrault, C., Pravossoudovitch, S., Virazel, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2006
Subjects
Failure analysis
Flash memory
Logic testing
Nonvolatile memory
Parallel programming
Random access memory
Tunneling
Uniform resource locators
Variable structure systems
Voltage control
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ISBN0780397266
9780780397262
DOI10.1109/DTIS.2006.1708721

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Summary:The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like flash. Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. In this paper, we present a complete analysis of a particular failure mechanism, referred as disturb phenomenon. Moreover, we analyze the efficiency of a particular test sequence to detect this disturb phenomenon. Finally we conclude on the interest to develop new test infrastructure well adapted to the eFlash environment
ISBN:0780397266
9780780397262
DOI:10.1109/DTIS.2006.1708721