Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units

Multi/many-core processors allow to handle path delay faults although the number of paths exponentially grows with the circuit size. This paper proposes an efficient path delay fault simulation that identifies all the robust and non-robust testable path delay faults for each test pattern. The simula...

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Bibliographic Details
Published in2014 IEEE 23rd Asian Test Symposium pp. 292 - 297
Main Authors Ali, Yussuf, Yamato, Yuta, Yoneda, Tomokazu, Hatayama, Kazumi, Inoue, Michiko
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2014
Subjects
Circuit faults
Delays
Integrated circuit modeling
Logic gates
Multicore processing
non-robust testable
path delay fault simulation
Program processors
robust testable
Robustness
SIMD
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Summary:Multi/many-core processors allow to handle path delay faults although the number of paths exponentially grows with the circuit size. This paper proposes an efficient path delay fault simulation that identifies all the robust and non-robust testable path delay faults for each test pattern. The simulation result is expressed by a scalable data structure only proportional to the numbers of gates and test patterns. The proposed simulation uses two types of parallelism, bit- and thread-parallelism, while considering efficient usage of multiple computing units and SIMD units which is resulting in a very fast simulation. Experimental results demonstrate the efficiency of the proposed method identifying all the robust and non-robust testable paths for a large number of test patterns. In addition, the simulation surpasses a commercial logic simulator which just processes a part of the proposed method.
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2014.61