Configurable 8T SRAM for Enbling in-Memory Computing

To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. This paper proposes a configurable 8T SRAM which can...

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Bibliographic Details
Published in2019 2nd International Conference on Communication Engineering and Technology (ICCET) pp. 139 - 142
Main Authors Chen, Han-Chun, Li, Jin-Fu, Hsu, Chun-Lung, Sun, Chi-Tien
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.04.2019
Subjects
Arrays
computing architecture
content addressable memory
Decoding
Multiplexing
Registers
SRAM cells
static random access memory
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Summary:To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. This paper proposes a configurable 8T SRAM which can provide the functions of ternary content address memory, left shift, and right shift in addition to the storage function. The method only needs to modify the peripheral circuitry of an 8 T SRAM. The Hspice simulator is used to verify configurable 8T SRAM using TSMC 0.18μm CMOS technology.
DOI:10.1109/ICCET.2019.8726871