Diminished offset current analysis in FinFET

• Published in: 2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy pp. 1 - 6
• Main Authors: Veshala, Mahender, Jatooth, Ramchander, Reddy, Kota Rajesh
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2013
• Subjects: DG-FET; DIBL; etches; FinFET; FinFETs; GIDL; hysteretic threshold; Logic gates; parasitic bipolar effect; roll-off; short channel effects; Silicon; Switches; Threshold voltage
• ISBN: 1467351504; 9781467351508
• DOI: 10.1109/AICERA-ICMiCR.2013.6575951

An architecture which has multi-gate or tri-gate architecture is called FinFET technology, deliver superior levels of scalability but design engineers face significant challenges in creating designs that optimize the promise of this exciting new technology. It is an attractive successor to the single gate MOSFET by merit of its superior electrostatic properties and comparative ease of manufacturability process. Inventing new device is always essential to improve the circuit performance; the total steps are more than usual MOSFET process, but the cost of material is less. Since it is more compact, using FinFET is economical. The leakage current due to DIBL (Drain Induced Barrier Lowering) was well suppressed and the roll-off of a FinFET is well controlled. An application of FinFET Technology has opened new development in Nano-technology. Simulation results prove that FinFET structure would be scalable down to lower technology. Formation of ultra thin fin enables suppressed short channel effects and which in turns decrease the leakage currents.