A systematic approach to SER estimation and solutions

This paper describes a method for estimating Soft Error Rate (SER) and a systematic approach to identifying SER solutions. Having a good SER estimate is the first step in identifying if a problem exists and what measures are necessary to solve the problem. In this paper, a high performance processor...

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Bibliographic Details
Published in2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual pp. 60 - 70
Main Authors Nguyen, H.T., Yagil, Y.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2003
Subjects
Alpha particles
Combinational circuits
Error analysis
Error correction
Guidelines
Latches
Logic
Neutrons
Single event upset
Space technology
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Summary:This paper describes a method for estimating Soft Error Rate (SER) and a systematic approach to identifying SER solutions. Having a good SER estimate is the first step in identifying if a problem exists and what measures are necessary to solve the problem. In this paper, a high performance processor is used as the base framework for discussion since it contains most, if not all, commonly used micro-architecture and circuit techniques associated with any state-of-the-art design. The framework provides a guideline for users to follow and to apply appropriate judgment to their particular problem. One major finding in this paper is that latches/flip-flops and combinational logic contribute significantly to the overall chip Failure-In-Time (FIT) rate. We also discuss potential SER techniques to combat this revelation.
ISBN:0780376498
9780780376496
DOI:10.1109/RELPHY.2003.1197722