99dBc/Hz@10kHz 1MHz-step dual-loop integer-N PLL with anti-mislocking frequency calibration for global navigation satellite system receiver

• Published in: 2011 IEEE International Symposium of Circuits and Systems (ISCAS) pp. 1876 - 1879
• Main Authors: Congyin Shi, Chuan Wang, Le Ye, Huailin Liao
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2011
• Subjects: Frequency control; Frequency synthesizers; Global Positioning System; Mixers; Phase locked loops; Phase noise; Synthesizers
• ISBN: 1424494737; 9781424494736
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2011.5937953

In this paper, a low in-band phase noise integer-N CMOS frequency synthesizer is proposed for global navigation satellite system (GNSS) receiver. The synthesizer adopts dual-loop architecture, which consists of a double-balanced mixer and two full PLL loops, to reduce the divide ratio so as to lower the in-band phase noise. It achieves 1MHz resolution and -99 dBc/Hz@10kHz with fixed reference clock of 10MHz, which is compatible to commercial atomic frequency sources. Moreover, a novel adaptive frequency calibration policy is implemented to avoid mis-locking at the unwanted mirror frequency. The PLL is fabricated in 0.18-μm CMOS technology, covers most GPS, Galileo and Beidou-II bands and was integrated in a GNSS receiver with 46MHz intermediate frequency (IF).