A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control

• Published in: 2018 IEEE International Solid - State Circuits Conference - (ISSCC) pp. 208 - 210
• Main Authors: Cho, Jin Hee, Kim, Jihwan, Lee, Woo Young, Lee, Dong Uk, Kim, Tae Kyun, Park, Heat Bit, Jeong, Chunseok, Park, Myeong-Jae, Baek, Seung Geun, Choi, Seokwoo, Yoon, Byung Kuk, Choi, Young Jae, Lee, Kyo Yun, Shim, Daeyong, Oh, Jonghoon, Kim, Jinkook, Lee, Seok-Hee
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2018
• Subjects: Bandwidth; Maintenance engineering; Random access memory; Spirals; Temperature sensors; Through-silicon vias; Timing
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2018.8310257

With the recent increasing interest in big data and artificial intelligence, there is an emerging demand for high-performance memory system with large density and high data-bandwidth. However, conventional DIMM-type memory has difficulty achieving more than 50GB/s due to its limited pin count and signal integrity issues. High-bandwidth memory (HBM) DRAM, with TSV technology and wide IOs, is a prominent solution to this problem, but it still has many limitations: including power consumption and reliability. This paper presents a power-efficient structure of TSVs with reliability and a cost-effective HBM DRAM core architecture.