A CT sigma-delta modulator with a hybrid loop filter and capacitive feedforward

• Published in: 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 1 - 4
• Main Authors: Jhin-Fang Huang, Yen-Jung Lin, Kun-Chieh Huang, Ron-Yi Liu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2011
• Subjects: CIFF; Clocks; CMOS integrated circuits; CMOS technology; Noise; sigma-delta modulator; Solids; Switches; WCDMA; ΣΔM
• ISBN: 9781612848563; 1612848567
• ISSN: 1548-3746; 1558-3899
• DOI: 10.1109/MWSCAS.2011.6026516

A CT (continuous-time) sigma-delta modulator (CT ΣΔM) clocked at 128 MHz with a hybrid active-passive loop filter is presented for WCDMA applications. This 5 th -order loop filter architecture mainly consists of two passive integrators and three active integrators. To erase the summation amplifier used in the CIFF (chain of integrators with weighted feedforward summation) topology, the capacitive feedforward structure is employed. In addition, local feedback resistors are formed as the bridge-T network to reduce the chip area. After chip being fabricated in TSMC 0.18 μm 1.8 V CMOS technology, the overall measured results have achieved dynamic range of 62 dB over a 2 MHz signal bandwidth, SNDR of 60.26 dB, IM3 of -48 dB and power dissipation of 9 mW. Including pads, the overall chip area is 0.642 (1.07 × 0.6) mm 2 .