RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation

This work presents a hybrid CMOS-RRAM integration of spiking nonvolatile computing-in-memory (nvCIM) processing engine (PE) that includes a 64Kb RRAM macro and a novel in situ nonlinear activation (ISNA) module. We integrate the computing controller and nonlinear activation function on-chip to compu...

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Bibliographic Details
Published in2019 Symposium on VLSI Technology pp. T86 - T87
Main Authors Yan, Bonan, Yang, Qing, Chen, Wei-Hao, Chang, Kung-Tang, Su, Jian-Wei, Hsu, Chien-Hua, Li, Sih-Han, Lee, Heng-Yuan, Sheu, Shyh-Shyuan, Ho, Mon-Shu, Wu, Qing, Chang, Meng-Fan, Chen, Yiran, Li, Hai
Format Conference Proceeding
LanguageEnglish
Published The Japan Society of Applied Physics 01.06.2019
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