RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation

This work presents a hybrid CMOS-RRAM integration of spiking nonvolatile computing-in-memory (nvCIM) processing engine (PE) that includes a 64Kb RRAM macro and a novel in situ nonlinear activation (ISNA) module. We integrate the computing controller and nonlinear activation function on-chip to compu...

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Published in2019 Symposium on VLSI Technology pp. T86 - T87
Main Authors Yan, Bonan, Yang, Qing, Chen, Wei-Hao, Chang, Kung-Tang, Su, Jian-Wei, Hsu, Chien-Hua, Li, Sih-Han, Lee, Heng-Yuan, Sheu, Shyh-Shyuan, Ho, Mon-Shu, Wu, Qing, Chang, Meng-Fan, Chen, Yiran, Li, Hai
Format Conference Proceeding
LanguageEnglish
Published The Japan Society of Applied Physics 01.06.2019
Subjects
activation precision
Analog-digital conversion
computing in memory
Current measurement
Engines
nonvolatile emerging memory
Power measurement
processing engine
RRAM
spiking
Synapses
Very large scale integration
Voltage measurement
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Summary:This work presents a hybrid CMOS-RRAM integration of spiking nonvolatile computing-in-memory (nvCIM) processing engine (PE) that includes a 64Kb RRAM macro and a novel in situ nonlinear activation (ISNA) module. We integrate the computing controller and nonlinear activation function on-chip to compute convolutional or fully-connected neural network. ISNA merges A/D conversion and activation computation by leveraging its nonlinear working region. This eliminates the need for additional circuits to realize nonlinearity and reduces area by 43.7x w.r.t. the ADC scheme. The activation precision of ISNA can be configured from 1 to 8 bits to balance throughput, accuracy and power efficiency. The measurement of 4-layer LeNet shows such optimization improves 23.1% of computing speed via compromising a 2.5% relative accuracy drop. The proposed nvCIM PE achieves 16.9 TOPS/W power efficiency and a maximum spike frequency of 99.24 MHz.
ISSN:2158-9682
DOI:10.23919/VLSIT.2019.8776485