Timing-constrained yield-driven redundant via insertion

In this paper, based on the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias...

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Bibliographic Details
Published inAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems pp. 1688 - 1691
Main Authors Jin-Tai Yan, Zhi-Wei Chen, Bo-Yi Chiang, Yu-Min Lee
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2008
Subjects
Benchmark testing
Computer science
Constraint optimization
Delay
Equivalent circuits
Integrated circuit modeling
Joining processes
Routing
Timing
Wire
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Summary:In this paper, based on the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion, the experimental results show that our proposed enhanced two-phase insertion approach can further reduce 0.006% total wire length on the average with the reduction of 0.0002% chip yield to maintain 100% timing constraints for the tested benchmarks.
ISBN:9781424423415
1424423414
DOI:10.1109/APCCAS.2008.4746363