System level jitter characterization of high speed I/O systems

• Published in: 2012 IEEE International Symposium on Electromagnetic Compatibility pp. 173 - 178
• Main Author: Oh, D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2012
• Subjects: Analytical models; Clocks; Jitter; Noise; Sensitivity; Timing; Transmitters
• ISBN: 9781467320610; 1467320617
• ISSN: 2158-110X
• DOI: 10.1109/ISEMC.2012.6351789

As I/O speed continues to increase; the contribution of device jitter to the overall timing error becomes increasingly significant in high-speed interfaces. Conventional deterministic jitter components, such as inter-symbol interference (ISI) and duty-cycle distortion (DCD), remain relatively constant in terms of bit time. Other uncorrelated jitter components, such as random jitter (RJ) and power supply noise induced jitter (PSIJ), become more critical, because they are relatively hard to reduce. To date, uncorrelated jitter has been primarily modeled at the device or component level. Little work has been done to characterize its impact at the system level. First, this paper illustrates the various system-level issues caused by uncorrelated jitter. Next, the concept of jitter amplification and cancellation, using a clock signal, is reviewed in detail. Then, we describe a statistical link-simulation methodology that can be used to analyze the system-level jitter behavior. (PSIJ is used to demonstrate the modelling of the jitter source and its propagation.) We conclude with the correlation between in-situ on-chip measurements, and the results of the simulation.