FPGA-implementation of a target detector for nonuniform samples

As we have seen in this paper, FPGAs are a good candidate for implementing compute-intensive algorithms. Although the processing frequency is more than 10 times lower, their capability to process multiple data channels in parallel compensates for it and gives them an advantage in relation to CPUs. B...

Full description

Saved in:
Bibliographic Details
Published in2017 18th International Radar Symposium (IRS) pp. 1 - 9
Main Authors Alicajic, Edo, Rugheimer, Christoph, Schmidt, Alexander, Particke, Florian, Mahr, Thomas
Format Conference Proceeding
LanguageEnglish
Published German Institute of Navigation-DGON 01.06.2017
Subjects
C++ languages
Computer architecture
Detectors
Doppler radar
Field programmable gate arrays
Microprocessors
Random access memory
Online AccessGet full text

Cover

More Information
Summary:As we have seen in this paper, FPGAs are a good candidate for implementing compute-intensive algorithms. Although the processing frequency is more than 10 times lower, their capability to process multiple data channels in parallel compensates for it and gives them an advantage in relation to CPUs. By comparing the results we see that the processing time was sped up by factor of 3 with 60% of the resources on the chip used, while consuming only 5 % electrical power of the CPU. Having these results in mind we have to mention the possibilities of the state of the art FPGAs that are currently available on the market. Some of them offer up to 12,000 DSP slices which is more than enough to process 2000 range cells in parallel.
ISSN:2155-5753
DOI:10.23919/IRS.2017.8008253