SEIFF: Soft Error Immune Flip-Flop for Mitigating Single Event Upset and Single Event Transient in 10 nm FinFET
This paper proposes soft error immune flip-flop (SEIFF) for mitigating single event upset (SEU) in flip-flops (FFs) and impact of single event transient (SET) in combinational-logic. SEIFF mitigates the SET without enlarging setup-time and delay; there is no overhead in circuit performance. Alpha an...
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Published in | 2019 IEEE International Reliability Physics Symposium (IRPS) pp. 1 - 6 |
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Main Authors | , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.03.2019
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Subjects | |
Online Access | Get full text |
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Summary: | This paper proposes soft error immune flip-flop (SEIFF) for mitigating single event upset (SEU) in flip-flops (FFs) and impact of single event transient (SET) in combinational-logic. SEIFF mitigates the SET without enlarging setup-time and delay; there is no overhead in circuit performance. Alpha and proton tests validate the mitigation efficiency in SEIFF manufactured on 10 nm FinFET technology. |
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ISSN: | 1938-1891 |
DOI: | 10.1109/IRPS.2019.8720513 |